roo_display
API Documentation for roo_display
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spi_reg.h
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1#pragma once
2
3#include "roo_backport.h"
4#include "roo_backport/byte.h"
5#include "roo_display/hal/spi_settings.h"
6#include "roo_io/data/byte_order.h"
7#include "soc/spi_reg.h"
8
9#if CONFIG_IDF_TARGET_ESP32
10#define ROO_DISPLAY_ESP32_SPI_DEFAULT_PORT 3
11#else
12#define ROO_DISPLAY_ESP32_SPI_DEFAULT_PORT 2
13#ifndef SPI_MOSI_DLEN_REG
14#define SPI_MOSI_DLEN_REG(x) SPI_MS_DLEN_REG(x)
15#endif
16#ifndef SPI_MISO_DLEN_REG
17#define SPI_MISO_DLEN_REG(x) SPI_MS_DLEN_REG(x)
18#endif
19#endif
20
21#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
22#define ROO_DISPLAY_SPI_CMD_UPDATE_REQUIRED 1
23#else
24#define ROO_DISPLAY_SPI_CMD_UPDATE_REQUIRED 0
25#endif
26
27#ifndef SPI_DMA_TX_ENA
28#ifdef SPI_DMA_TX_EN
29#define SPI_DMA_TX_ENA SPI_DMA_TX_EN
30#endif
31#endif
32
33#ifndef SPI_TRANS_DONE_INT_ENA
34#ifdef SPI_OUT_EOF_INT_ENA
35#define SPI_TRANS_DONE_INT_ENA SPI_OUT_EOF_INT_ENA
36#elif defined(SPI_OUT_DONE_INT_ENA)
37#define SPI_TRANS_DONE_INT_ENA SPI_OUT_DONE_INT_ENA
38#endif
39#endif
40
41#ifndef SPI_TRANS_DONE_INT_CLR
42#ifdef SPI_OUT_EOF_INT_CLR
43#define SPI_TRANS_DONE_INT_CLR SPI_OUT_EOF_INT_CLR
44#elif defined(SPI_OUT_DONE_INT_CLR)
45#define SPI_TRANS_DONE_INT_CLR SPI_OUT_DONE_INT_CLR
46#endif
47#endif
48
49#ifndef SPI_TRANS_DONE_INT_ST
50#ifdef SPI_OUT_EOF_INT_ST
51#define SPI_TRANS_DONE_INT_ST SPI_OUT_EOF_INT_ST
52#elif defined(SPI_OUT_DONE_INT_ST)
53#define SPI_TRANS_DONE_INT_ST SPI_OUT_DONE_INT_ST
54#endif
55#endif
56
57#ifndef ROO_TESTING
58
59namespace roo_display {
60namespace esp32 {
61
62// Enters the read-write mode.
63inline void SpiSetReadWriteMode(uint8_t spi_port)
64 __attribute__((always_inline));
65
66// Enters the write-only mode.
67inline void SpiSetWriteOnlyMode(uint8_t spi_port)
68 __attribute__((always_inline));
69
70// Initiates a polling (non-ISR) SPI operation.
71inline void SpiTxStart(uint8_t spi_port) __attribute__((always_inline));
72
73// Waits for the current SPI operation, if any, to complete.
74inline void SpiTxWait(uint8_t spi_port) __attribute__((always_inline));
75
76// Returns true when the SPI DMA transfer-done interrupt is pending.
77inline bool SpiDmaTransferDoneIntPending(uint8_t spi_port)
78 __attribute__((always_inline));
79
80// Clears the SPI DMA transfer-done interrupt.
81inline void SpiDmaTransferDoneIntClear(uint8_t spi_port)
82 __attribute__((always_inline));
83
84// Enables the SPI DMA transfer-done interrupt.
85inline void SpiDmaTransferDoneIntEnable(uint8_t spi_port)
86 __attribute__((always_inline));
87
88// Disables the SPI DMA transfer-done interrupt.
89inline void SpiDmaTransferDoneIntDisable(uint8_t spi_port)
90 __attribute__((always_inline));
91
92// Enables SPI DMA TX.
93inline void SpiDmaTxEnable(uint8_t spi_port)
94 __attribute__((always_inline));
95
96// Disables SPI DMA TX.
97inline void SpiDmaTxDisable(uint8_t spi_port)
98 __attribute__((always_inline));
99
100// Sets the number of bytes in the output buffer for the next SPI operation.
101inline void SpiSetOutBufferSize(uint8_t spi_port, int len)
102 __attribute__((always_inline));
103
104// Sets the number of bytes in the output and input buffers for the next SPI
105// operation.
106inline void SpiSetTxBufferSize(uint8_t spi_port, int len)
107 __attribute__((always_inline));
108
109// Writes 4 bytes to the output registers from the provided uint32 value
110// (assumed byte-swapped to big-endian).
111inline void SpiWrite4(uint8_t spi_port, uint32_t d32)
112 __attribute__((always_inline));
113
114// Reads 4 bytes from the output registers.
115inline uint32_t SpiRead4(uint8_t spi_port) __attribute__((always_inline));
116
117// Writes 64 bytes to the output registers from the 32-bit aligned input buffer.
118inline void SpiWrite64Aligned(uint8_t spi_port, const roo::byte* data)
119 __attribute__((always_inline));
120
121// Writes up to 64 bytes to the output registers, from the 32-bit aligned
122// buffer.
123inline void SpiWriteUpTo64Aligned(uint8_t spi_port, const roo::byte* data,
124 int len) __attribute__((always_inline));
125
126// Fills 64 bytes of the output registers with the specified 32-bit value.
127inline void SpiFill64(uint8_t spi_port, uint32_t d32)
128 __attribute__((always_inline));
129
130// Fills output registers with 1-64 bytes, provided in the 32-bit aligned
131// buffer.
132inline void SpiFillUpTo64(uint8_t spi_port, uint32_t d32, int len)
133 __attribute__((always_inline));
134
135// Fills output registers with up to 60 bytes, repeating the specified 12-byte
136// pattern.
137inline void SpiFill60(uint8_t spi_port, uint32_t d0, uint32_t d1, uint32_t d2)
138 __attribute__((always_inline));
139
140// Fills output registers with 60 bytes, 5x repeating the specified 12-byte
141// pattern.
142inline void SpiFillUpTo60(uint8_t spi_port, uint32_t d0, uint32_t d1,
143 uint32_t d2, int len) __attribute__((always_inline));
144
145// Implementation below.
146
147inline void SpiTxWait(uint8_t spi_port) {
148 while (READ_PERI_REG(SPI_CMD_REG(spi_port)) & SPI_USR) {
149 }
150}
151
156
160
164
168
172
176
177inline void SpiTxStart(uint8_t spi_port) {
178#if ROO_DISPLAY_SPI_CMD_UPDATE_REQUIRED
179 SET_PERI_REG_MASK(SPI_CMD_REG(spi_port), SPI_UPDATE);
180 while (READ_PERI_REG(SPI_CMD_REG(spi_port)) & SPI_UPDATE) {
181 }
182#endif
183
184 // SET_PERI_REG_MASK(SPI_CMD_REG(spi_port), SPI_USR);
185 // The 'correct' way to set the SPI_USR would be to set just the single bit,
186 // as in the commented-out code above. But the remaining bits of this register
187 // are unused (marked 'reserved'; see
188 // https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf
189 // page 131). Unconditionally setting the entire register brings significant
190 // performance improvements.
191 WRITE_PERI_REG(SPI_CMD_REG(spi_port), SPI_USR);
192}
193
197
198inline void SpiSetTxBufferSize(uint8_t spi_port, int len) {
199 WRITE_PERI_REG(SPI_MOSI_DLEN_REG(spi_port), (len << 3) - 1);
200#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
201 WRITE_PERI_REG(SPI_MISO_DLEN_REG(spi_port), (len << 3) - 1);
202#endif
203}
204
209
213
233
237
241
242inline void SpiWriteUpTo64Aligned(uint8_t spi_port, const roo::byte* data,
243 int len) {
244 const uint32_t* d32 = reinterpret_cast<const uint32_t*>(data);
245 do {
246 WRITE_PERI_REG(SPI_W0_REG(spi_port), d32[0]);
247 if (len <= 4) break;
248 WRITE_PERI_REG(SPI_W1_REG(spi_port), d32[1]);
249 if (len <= 8) break;
250 WRITE_PERI_REG(SPI_W2_REG(spi_port), d32[2]);
251 if (len <= 12) break;
252 WRITE_PERI_REG(SPI_W3_REG(spi_port), d32[3]);
253 if (len <= 16) break;
254 WRITE_PERI_REG(SPI_W4_REG(spi_port), d32[4]);
255 if (len <= 20) break;
256 WRITE_PERI_REG(SPI_W5_REG(spi_port), d32[5]);
257 if (len <= 24) break;
258 WRITE_PERI_REG(SPI_W6_REG(spi_port), d32[6]);
259 if (len <= 28) break;
260 WRITE_PERI_REG(SPI_W7_REG(spi_port), d32[7]);
261 if (len <= 32) break;
262 WRITE_PERI_REG(SPI_W8_REG(spi_port), d32[8]);
263 if (len <= 36) break;
264 WRITE_PERI_REG(SPI_W9_REG(spi_port), d32[9]);
265 if (len <= 40) break;
266 WRITE_PERI_REG(SPI_W10_REG(spi_port), d32[10]);
267 if (len <= 44) break;
268 WRITE_PERI_REG(SPI_W11_REG(spi_port), d32[11]);
269 if (len <= 48) break;
270 WRITE_PERI_REG(SPI_W12_REG(spi_port), d32[12]);
271 if (len <= 52) break;
272 WRITE_PERI_REG(SPI_W13_REG(spi_port), d32[13]);
273 if (len <= 56) break;
274 WRITE_PERI_REG(SPI_W14_REG(spi_port), d32[14]);
275 if (len <= 60) break;
276 WRITE_PERI_REG(SPI_W15_REG(spi_port), d32[15]);
277 } while (false);
278}
279
298
299inline void SpiFillUpTo64(uint8_t spi_port, uint32_t d32, int len) {
300 do {
301 WRITE_PERI_REG(SPI_W0_REG(spi_port), d32);
302 if (len <= 4) break;
303 WRITE_PERI_REG(SPI_W1_REG(spi_port), d32);
304 if (len <= 8) break;
305 WRITE_PERI_REG(SPI_W2_REG(spi_port), d32);
306 if (len <= 12) break;
307 WRITE_PERI_REG(SPI_W3_REG(spi_port), d32);
308 if (len <= 16) break;
309 WRITE_PERI_REG(SPI_W4_REG(spi_port), d32);
310 if (len <= 20) break;
311 WRITE_PERI_REG(SPI_W5_REG(spi_port), d32);
312 if (len <= 24) break;
313 WRITE_PERI_REG(SPI_W6_REG(spi_port), d32);
314 if (len <= 28) break;
315 WRITE_PERI_REG(SPI_W7_REG(spi_port), d32);
316 if (len <= 32) break;
317 WRITE_PERI_REG(SPI_W8_REG(spi_port), d32);
318 if (len <= 36) break;
319 WRITE_PERI_REG(SPI_W9_REG(spi_port), d32);
320 if (len <= 40) break;
321 WRITE_PERI_REG(SPI_W10_REG(spi_port), d32);
322 if (len <= 44) break;
323 WRITE_PERI_REG(SPI_W11_REG(spi_port), d32);
324 if (len <= 48) break;
325 WRITE_PERI_REG(SPI_W12_REG(spi_port), d32);
326 if (len <= 52) break;
327 WRITE_PERI_REG(SPI_W13_REG(spi_port), d32);
328 if (len <= 56) break;
329 WRITE_PERI_REG(SPI_W14_REG(spi_port), d32);
330 if (len <= 60) break;
331 WRITE_PERI_REG(SPI_W15_REG(spi_port), d32);
332 } while (false);
333}
334
352
353inline void SpiFillUpTo60(uint8_t spi_port, uint32_t d0, uint32_t d1,
354 uint32_t d2, int len) {
355 do {
356 WRITE_PERI_REG(SPI_W0_REG(spi_port), d0);
357 if (len <= 4) break;
358 WRITE_PERI_REG(SPI_W1_REG(spi_port), d1);
359 if (len <= 8) break;
360 WRITE_PERI_REG(SPI_W2_REG(spi_port), d2);
361 if (len <= 12) break;
362 WRITE_PERI_REG(SPI_W3_REG(spi_port), d0);
363 if (len <= 16) break;
364 WRITE_PERI_REG(SPI_W4_REG(spi_port), d1);
365 if (len <= 20) break;
366 WRITE_PERI_REG(SPI_W5_REG(spi_port), d2);
367 if (len <= 24) break;
368 WRITE_PERI_REG(SPI_W6_REG(spi_port), d0);
369 if (len <= 28) break;
370 WRITE_PERI_REG(SPI_W7_REG(spi_port), d1);
371 if (len <= 32) break;
372 WRITE_PERI_REG(SPI_W8_REG(spi_port), d2);
373 if (len <= 36) break;
374 WRITE_PERI_REG(SPI_W9_REG(spi_port), d0);
375 if (len <= 40) break;
376 WRITE_PERI_REG(SPI_W10_REG(spi_port), d1);
377 if (len <= 44) break;
378 WRITE_PERI_REG(SPI_W11_REG(spi_port), d2);
379 if (len <= 48) break;
380 WRITE_PERI_REG(SPI_W12_REG(spi_port), d0);
381 if (len <= 52) break;
382 WRITE_PERI_REG(SPI_W13_REG(spi_port), d1);
383 if (len <= 56) break;
384 WRITE_PERI_REG(SPI_W14_REG(spi_port), d2);
385 } while (false);
386}
387
388} // namespace esp32
389} // namespace roo_display
390
391#endif // ROO_TESTING
roo_display::esp32::SpiSetWriteOnlyMode
void SpiSetWriteOnlyMode(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:210
roo_display::esp32::SpiFill60
void SpiFill60(uint8_t spi_port, uint32_t d0, uint32_t d1, uint32_t d2) __attribute__((always_inline))
Definition spi_reg.h:335
roo_display::esp32::SpiDmaTransferDoneIntDisable
void SpiDmaTransferDoneIntDisable(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:165
roo_display::esp32::SpiFill64
void SpiFill64(uint8_t spi_port, uint32_t d32) __attribute__((always_inline))
Definition spi_reg.h:280
roo_display::esp32::SpiDmaTransferDoneIntClear
void SpiDmaTransferDoneIntClear(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:157
roo_display::esp32::SpiWriteUpTo64Aligned
void SpiWriteUpTo64Aligned(uint8_t spi_port, const roo::byte *data, int len) __attribute__((always_inline))
Definition spi_reg.h:242
roo_display::esp32::SpiDmaTxDisable
void SpiDmaTxDisable(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:173
roo_display::esp32::SpiTxWait
void SpiTxWait(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:147
roo_display::esp32::SpiSetOutBufferSize
void SpiSetOutBufferSize(uint8_t spi_port, int len) __attribute__((always_inline))
Definition spi_reg.h:194
roo_display::esp32::SpiTxStart
void SpiTxStart(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:177
roo_display::esp32::SpiDmaTransferDoneIntEnable
void SpiDmaTransferDoneIntEnable(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:161
roo_display::esp32::SpiWrite4
void SpiWrite4(uint8_t spi_port, uint32_t d32) __attribute__((always_inline))
Definition spi_reg.h:234
roo_display::esp32::SpiRead4
uint32_t SpiRead4(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:238
roo_display::esp32::SpiSetTxBufferSize
void SpiSetTxBufferSize(uint8_t spi_port, int len) __attribute__((always_inline))
Definition spi_reg.h:198
roo_display::esp32::SpiDmaTransferDoneIntPending
bool SpiDmaTransferDoneIntPending(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:152
roo_display::esp32::SpiSetReadWriteMode
void SpiSetReadWriteMode(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:205
roo_display::esp32::SpiWrite64Aligned
void SpiWrite64Aligned(uint8_t spi_port, const roo::byte *data) __attribute__((always_inline))
Definition spi_reg.h:214
roo_display::esp32::SpiDmaTxEnable
void SpiDmaTxEnable(uint8_t spi_port) __attribute__((always_inline))
Definition spi_reg.h:169
roo_display::esp32::SpiFillUpTo60
void SpiFillUpTo60(uint8_t spi_port, uint32_t d0, uint32_t d1, uint32_t d2, int len) __attribute__((always_inline))
Definition spi_reg.h:353
roo_display::esp32::SpiFillUpTo64
void SpiFillUpTo64(uint8_t spi_port, uint32_t d32, int len) __attribute__((always_inline))
Definition spi_reg.h:299
roo_display
Defines 140 opaque HTML named colors.
Definition roo_display.cpp:7
SPI_MISO_DLEN_REG
#define SPI_MISO_DLEN_REG(x)
Definition spi_reg.h:17
SPI_MOSI_DLEN_REG
#define SPI_MOSI_DLEN_REG(x)
Definition spi_reg.h:14
spi_settings.h
roo_display::BlendOp
Definition blending.h:200